A PLL (phase locked loop) circuit is used in a circuit for adjusting a clock period. FIG. 27 illustrates a conventional PLL circuit. Referring to FIG. 27, a phase frequency detector. (PFD) 319 receives an external clock 324 and a signal supplied from a frequency divider 323 that receives an output of a voltage-controlled oscillator 322. A charge pump 320 receives a up signal 325 and a down signal 326 both output from a phase frequency detector (PFD) 319 to output a voltage corresponding to a phase difference. A loop filter receives the voltage from the charging pump 320 to output smoothed voltage which is supplied as a control voltage to the voltage-controlled oscillator (VCO) 322. An output clock signal of a frequency corresponding to the control voltage from the voltage-controlled oscillator (VCO) 322 is fed to a frequency divider 323.
For example, there is proposed in JP Patent Kokai JP-A-11-284497 a programmable delay generator in which a ramp waveform voltage for determining a delay time and a threshold voltage can be generated by circuits of the same structure and can be independently set so that it is capable of generating the delay time of a fractional number, a numerator and a denominator of which can be set, a frequency synthesizer which, by phase-interpolating output pulses of an accumulator using a programmable delay generator, is able to generate an adjustment-free low-spurious output signal, a multiplication circuit employing a programmable delay generator, a duty ratio converter circuit employing the programmable delay generator as an output pulse width setting delay generator, and a PLL frequency synthesizer having the programmable delay generator inserted between the frequency divider and a phase comparator.